浏览代码

riscv64, trap: fix kernel space trap returns

On riscv64 platforms, we load the kernel tp only if we've come from U
mode to reduce overhead. But we would restore the tp saved in
TrapContext even if we are returning to kernel space, which causes
problems because the default tp is zero.

We should save kernel tp register to the field in TrapContext structs
when we set privilege mode to kernel.

Signed-off-by: greatbridf <greatbridf@icloud.com>
greatbridf 6 月之前
父节点
当前提交
6b152c74dd
共有 1 个文件被更改,包括 9 次插入1 次删除
  1. 9 1
      crates/eonix_hal/src/arch/riscv64/trap/trap_context.rs

+ 9 - 1
crates/eonix_hal/src/arch/riscv64/trap/trap_context.rs

@@ -224,7 +224,15 @@ impl RawTrapContext for TrapContext {
     fn set_user_mode(&mut self, user: bool) {
         match user {
             true => self.sstatus.set_spp(SPP::User),
-            false => self.sstatus.set_spp(SPP::Supervisor),
+            false => {
+                unsafe {
+                    core::arch::asm!(
+                        "mv {}, tp",
+                        out(reg) self.regs.tp,
+                    );
+                };
+                self.sstatus.set_spp(SPP::Supervisor);
+            }
         }
     }