x86, hal: support loading kernel image up to 14M

Still use only one kernel page table: use huge TLBs for all but the last
2M. Map those in the bootstrap code with a loop and then PTEs for the
rest. Theoretically, this way we can support up to kernel images with up
to 1G in size. Keep the image small for now.

Signed-off-by: greatbridf <greatbridf@icloud.com>

crates/eonix_hal/src/arch/x86_64/bootstrap.rs

@@ -409,17 +409,38 @@ global_asm!(
         mov ${KERNEL_PD_KIMAGE}, %esi
         call fill_pxe
 
-        # PDE 0xff0
+        # PDE 0xfc0 ~ ?
         mov ${KERNEL_PD_KIMAGE}, %edi
-        lea 0xff0(%edi), %edi
-        mov ${KERNEL_PT_KIMAGE}, %esi # 0x104000
+        mov ${KERNEL_IMAGE_PADDR}, %esi
+        lea 0xfc0(%edi), %edi
+
+        mov ${KIMAGE_PAGES}, %ecx
+        shr $9, %ecx                # 2M blocks
+
+        or ${PA_PS}, %ebx
+
+    2:
+        test %ecx, %ecx
+        jz 2f
+
+        call fill_pxe
+        lea 8(%edi), %edi
+        add $0x200000, %esi
+        dec %ecx
+        jmp 2b
+
+    2:
+        and $(~{PA_PS}), %ebx
+        push %esi
+        mov ${KERNEL_PT_KIMAGE}, %esi
         call fill_pxe
 
         # fill PT (kernel image)
         mov ${KERNEL_PT_KIMAGE}, %edi
-        mov ${KERNEL_IMAGE_PADDR}, %esi
+        pop %esi
 
         mov ${KIMAGE_PAGES}, %ecx
+        and $511, %ecx
 
     2:
         call fill_pxe
@@ -454,10 +475,12 @@ global_asm!(
     # %esi: page physical address
     # %edi: page x entry address
     fill_pxe:
+        push %eax
         lea (%ebx, %esi, 1), %eax
         mov %eax, (%edi)
         mov %edx, 4(%edi)
 
+        pop %eax
         ret
 
     .code64

crates/eonix_hal/src/arch/x86_64/memory.x

@@ -2,7 +2,7 @@ MEMORY {
     LOWMEM : org = 0x0000000000000000, len = 1M
     VDSO   : org = 0x00007f0000000000, len = 4K
     KBSS   : org = 0xffffffffc0200000, len = 2M
-    KIMAGE : org = 0xffffffffffc00000, len = 2M
+    KIMAGE : org = 0xffffffffff000000, len = 14M
 }
 
 REGION_ALIAS("REGION_TEXT", KIMAGE);