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@@ -1,48 +1,152 @@
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-use core::pin::Pin;
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-
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+use super::{config::platform::virt::*, fdt::FDT, fence::memory_barrier, mm::ArchPhysAccess};
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use crate::arch::time;
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-
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-use super::config::platform::virt::*;
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+use core::{pin::Pin, ptr::NonNull};
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+use eonix_mm::address::{PAddr, PhysAccess};
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+use eonix_sync_base::LazyLock;
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use riscv::register::sie;
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-use riscv_peripheral::{
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- aclint::{Clint, CLINT},
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- plic::{Plic, PLIC},
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-};
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use sbi::SbiError;
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-#[derive(Clone, Copy)]
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-struct ArchPlic;
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+const PRIORITY_OFFSET: usize = 0x0;
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+const PENDING_OFFSET: usize = 0x1000;
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-#[derive(Clone, Copy)]
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-struct ArchClint;
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+const ENABLE_OFFSET: usize = 0x2000;
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+const THRESHOLD_OFFSET: usize = 0x200000;
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+const CLAIM_COMPLETE_OFFSET: usize = 0x200004;
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-unsafe impl Plic for ArchPlic {
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- const BASE: usize = PLIC_BASE;
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-}
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+const ENABLE_STRIDE: usize = 0x80;
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+const CONTEXT_STRIDE: usize = 0x1000;
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+
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+static PLIC_BASE: LazyLock<PAddr> = LazyLock::new(|| {
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+ let plic = FDT
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+ .find_compatible(&["riscv,plic0", "riscv,plic1"])
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+ .expect("Failed to find PLIC in FDT");
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+
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+ let reg = plic
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+ .reg()
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+ .expect("PLIC node has no reg property")
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+ .next()
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+ .expect("PLIC reg property is empty");
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+
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+ PAddr::from(reg.starting_address as usize)
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+});
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-unsafe impl Clint for ArchClint {
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- const BASE: usize = CLINT_BASE;
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- const MTIME_FREQ: usize = CPU_FREQ_HZ as usize;
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+pub struct PLIC {
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+ enable: NonNull<u32>,
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+ threshold: NonNull<u32>,
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+ claim_complete: NonNull<u32>,
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}
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-/// Architecture-specific interrupt control block.
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pub struct InterruptControl {
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- clint: CLINT<ArchClint>,
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+ pub plic: PLIC,
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+}
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+
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+impl PLIC {
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+ fn new(cpuid: usize) -> Self {
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+ let base = *PLIC_BASE.get();
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+
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+ let enable = PAddr::from(base + (cpuid * 2 + 1) * ENABLE_STRIDE + ENABLE_OFFSET);
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+ let threshold = PAddr::from(base + (cpuid * 2 + 1) * CONTEXT_STRIDE + THRESHOLD_OFFSET);
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+ let claim_complete =
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+ PAddr::from(base + (cpuid * 2 + 1) * CONTEXT_STRIDE + CLAIM_COMPLETE_OFFSET);
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+
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+ unsafe {
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+ // SAFETY: The PLIC registers are memory-mapped and placed at specific addresses.
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+ // We are pretty sure that the addresses are valid.
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+ Self {
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+ enable: ArchPhysAccess::as_ptr(enable),
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+ threshold: ArchPhysAccess::as_ptr(threshold),
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+ claim_complete: ArchPhysAccess::as_ptr(claim_complete),
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+ }
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+ }
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+ }
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+
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+ pub fn set_threshold(&self, threshold: u32) {
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+ unsafe {
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+ self.threshold.write_volatile(threshold);
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+ }
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+ }
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+
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+ pub fn set_priority(&self, interrupt: usize, priority: u32) {
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+ let priority_ptr = unsafe {
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+ // SAFETY: The PLIC priority register is memory-mapped and placed at a specific address.
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+ // We are pretty sure that the address is valid.
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+ ArchPhysAccess::as_ptr(
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+ *PLIC_BASE.get() + PRIORITY_OFFSET + interrupt * size_of::<u32>(),
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+ )
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+ };
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+
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+ memory_barrier();
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+
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+ unsafe {
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+ priority_ptr.write_volatile(priority);
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+ }
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+
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+ memory_barrier();
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+ }
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+
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+ pub fn claim_interrupt(&self) -> Option<usize> {
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+ match unsafe { self.claim_complete.read_volatile() } {
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+ 0 => None,
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+ interrupt => Some(interrupt as usize),
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+ }
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+ }
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+
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+ pub fn complete_interrupt(&self, interrupt: usize) {
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+ unsafe {
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+ self.claim_complete.write_volatile(interrupt as u32);
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+ }
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+ }
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+
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+ pub fn enable_interrupt(&self, interrupt: usize) {
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+ debug_assert!(interrupt < 1024, "Interrupt number out of range");
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+
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+ let enable_ptr = unsafe {
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+ // SAFETY: Interrupt number is guaranteed to be less than 1024,
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+ // so we won't overflow the enable register array.
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+ self.enable.add(interrupt / 32)
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+ };
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+
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+ let bit = 1 << (interrupt % 32);
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+ unsafe {
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+ enable_ptr.write_volatile(enable_ptr.read_volatile() | bit);
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+ }
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+ }
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+
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+ pub fn disable_interrupt(&self, interrupt: usize) {
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+ let enable_ptr = unsafe {
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+ // SAFETY: Interrupt number is guaranteed to be less than 1024,
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+ // so we won't overflow the enable register array.
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+ self.enable.add(interrupt / 32)
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+ };
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+
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+ let bit = 1 << (interrupt % 32);
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+ unsafe {
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+ enable_ptr.write_volatile(enable_ptr.read_volatile() & !bit);
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+ }
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+ }
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}
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impl InterruptControl {
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/// # Safety
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/// should be called only once.
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- pub(crate) fn new() -> Self {
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+ pub(crate) fn new(cpuid: usize) -> Self {
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Self {
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- clint: CLINT::new(),
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+ plic: PLIC::new(cpuid),
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}
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}
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- pub fn init(self: Pin<&mut Self>) {}
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-}
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+ pub fn init(self: Pin<&mut Self>) {
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+ self.plic.set_threshold(0);
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+
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+ // TODO: We should enable interrupts only when we register a handler.
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+ for i in 0..32 {
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+ self.plic.set_priority(i, 1);
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+ self.plic.enable_interrupt(i);
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+ }
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-pub fn enable_timer_interrupt() {
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- unsafe { sie::set_stimer() };
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- time::set_next_timer();
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+ unsafe {
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+ sie::set_stimer();
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+ sie::set_sext();
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+ }
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+ }
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}
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