fix(hal): fix riscv enable/disable_irq

crates/eonix_hal/src/arch/riscv64/trap/mod.rs

@@ -11,6 +11,7 @@ use eonix_hal_traits::{
     trap::{IrqState as IrqStateTrait, TrapReturn},
 };
 use riscv::register::sie::Sie;
+use riscv::register::sstatus::{self, Sstatus};
 use riscv::register::stvec::TrapMode;
 use riscv::register::{scause, sepc, stval};
 use riscv::{
@@ -318,12 +319,12 @@ pub fn setup_trap() {
 }
 
 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
-pub struct IrqState(Sie);
+pub struct IrqState(Sstatus);
 
 impl IrqState {
     #[inline]
     pub fn save() -> Self {
-        IrqState(sie::read())
+        IrqState(sstatus::read())
     }
 }
 
@@ -331,7 +332,7 @@ impl IrqStateTrait for IrqState {
     fn restore(self) {
         let Self(state) = self;
         unsafe {
-            sie::write(state);
+            sstatus::write(state);
         }
     }
 }
@@ -339,18 +340,14 @@ impl IrqStateTrait for IrqState {
 #[inline]
 pub fn disable_irqs() {
     unsafe {
-        sie::clear_sext();
-        sie::clear_stimer();
-        sie::clear_ssoft();
+        sstatus::clear_sie();
     }
 }
 
 #[inline]
 pub fn enable_irqs() {
     unsafe {
-        sie::set_sext();
-        sie::set_stimer();
-        sie::set_ssoft();
+        sstatus::set_sie();
     }
 }