x86, TLS: adapt for the new TLS design

TLS should be a kernel feature instead of HAL work. Maybe we should
provide a more native interface for x86?

The changes should have been included in the commit. Pick them in now.

Fixes: 9a0eeb00ae79 ("tls: rework of arch's UserTLS design")
Signed-off-by: greatbridf <greatbridf@icloud.com>

crates/eonix_hal/src/arch/x86_64/cpu.rs

@@ -35,17 +35,6 @@ pub(crate) struct TSS {
     _pinned: PhantomPinned,
 }
 
-#[derive(Debug, Clone)]
-pub enum UserTLS {
-    /// TODO: This is not used yet.
-    #[allow(dead_code)]
-    TLS64(u64),
-    TLS32 {
-        base: u64,
-        desc: GDTEntry,
-    },
-}
-
 /// Architecture-specific cpu status data.
 pub struct CPU {
     cpuid: usize,
@@ -54,24 +43,6 @@ pub struct CPU {
     interrupt: InterruptControl,
 }
 
-impl UserTLS {
-    /// # Return
-    /// Returns the TLS descriptor and the index of the TLS segment.
-    pub fn new32(
-        base: u32, limit: u32, is_limit_in_pages: bool,
-    ) -> (Self, u32) {
-        let flags = if is_limit_in_pages { 0xc } else { 0x4 };
-
-        (
-            Self::TLS32 {
-                base: base as u64,
-                desc: GDTEntry::new(base, limit, 0xf2, flags),
-            },
-            7,
-        )
-    }
-}
-
 impl CPU {
     pub fn new() -> Self {
         let (interrupt_control, cpuid) = InterruptControl::new();
@@ -126,18 +97,14 @@ impl CPU {
         }
     }
 
-    pub fn set_tls32(self: Pin<&mut Self>, user_tls: &UserTLS) {
-        let UserTLS::TLS32 { desc, base } = user_tls else {
-            unimplemented!("TLS64 is not supported yet")
-        };
-
+    pub fn set_tls32(self: Pin<&mut Self>, desc: GDTEntry, base: u64) {
         unsafe {
             // SAFETY: We don't move the GDT object.
-            self.get_unchecked_mut().gdt.set_tls32(*desc);
+            self.get_unchecked_mut().gdt.set_tls32(desc);
         }
 
         const IA32_KERNEL_GS_BASE: u32 = 0xc0000102;
-        wrmsr(IA32_KERNEL_GS_BASE, *base);
+        wrmsr(IA32_KERNEL_GS_BASE, base);
     }
 
     pub fn cpuid(&self) -> usize {

crates/eonix_hal/src/arch/x86_64/gdt.rs

@@ -33,6 +33,14 @@ impl GDTEntry {
         GDTEntry(entry)
     }
 
+    pub const fn new_tls(base: u32, limit_in_bytes: u32) -> Self {
+        Self::new(base, limit_in_bytes, 0xf2, 0x4)
+    }
+
+    pub const fn new_tls_page_limit(base: u32, limit_in_pages: u32) -> Self {
+        Self::new(base, limit_in_pages, 0xf2, 0xc)
+    }
+
     pub const fn new_ldt(base: u64, limit: u32) -> [Self; 2] {
         let first = Self::new(base as u32, limit, 0x82, 0x0);
         let second = Self(base >> 32);
@@ -48,7 +56,7 @@ impl GDTEntry {
 
 impl GDT {
     const LEN: usize = 10;
-    const TLS32_INDEX: usize = 7;
+    pub const TLS32_INDEX: usize = 7;
     const TSS_INDEX: usize = 8;
 
     pub fn new() -> Self {