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@@ -0,0 +1,112 @@
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+use super::{GDT_OBJECT, TSS_OBJECT};
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+use crate::{
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+ kernel::{
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+ mem::{
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+ paging::Page,
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+ phys::{CachedPP, PhysPtr as _},
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+ },
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+ smp,
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+ },
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+ println_debug, println_info,
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+ sync::preempt,
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+};
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+use arch::{
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+ task::{pause, rdmsr},
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+ x86_64::{gdt::GDT, task::TSS},
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+};
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+use core::{
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+ arch::asm,
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+ sync::atomic::{AtomicU32, AtomicUsize, Ordering},
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+};
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+
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+unsafe fn init_gdt_tss_thiscpu() {
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+ preempt::disable();
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+ let gdt_ref = unsafe { GDT_OBJECT.as_mut() };
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+ let tss_ref = unsafe { TSS_OBJECT.as_mut() };
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+ *gdt_ref = Some(GDT::new());
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+ *tss_ref = Some(TSS::new());
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+
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+ if let Some(gdt) = gdt_ref.as_mut() {
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+ if let Some(tss) = tss_ref.as_mut() {
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+ gdt.set_tss(tss as *mut _ as u64);
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+ } else {
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+ panic!("TSS is not initialized");
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+ }
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+
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+ unsafe { gdt.load() };
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+ } else {
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+ panic!("GDT is not initialized");
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+ }
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+
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+ preempt::enable();
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+}
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+
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+pub unsafe fn init_cpu() {
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+ arch::x86_64::io::enable_sse();
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+
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+ let area = smp::alloc_percpu_area();
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+ smp::set_percpu_area(area);
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+ init_gdt_tss_thiscpu();
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+}
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+
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+#[no_mangle]
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+pub static BOOT_SEMAPHORE: AtomicU32 = AtomicU32::new(0);
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+#[no_mangle]
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+pub static BOOT_STACK: AtomicUsize = AtomicUsize::new(0);
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+
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+pub static AP_COUNT: AtomicUsize = AtomicUsize::new(0);
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+
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+#[no_mangle]
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+pub unsafe extern "C" fn ap_entry(_stack_start: u64) {
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+ init_cpu();
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+ let cpuid = AP_COUNT.fetch_add(1, Ordering::Release);
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+ println_debug!("AP{} started", cpuid);
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+
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+ // TODO!!!!!: Set up LAPIC and timer.
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+
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+ // TODO!!!!!: Set up idle task.
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+
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+ // TODO!!!!!: Free the stack before switching to idle task.
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+
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+ loop {}
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+}
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+
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+pub unsafe fn bootstrap_cpus() {
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+ let apic_base = rdmsr(0x1b);
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+ assert_eq!(apic_base & 0x800, 0x800, "LAPIC not enabled");
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+ assert_eq!(apic_base & 0x100, 0x100, "Is not bootstrap processor");
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+
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+ let apic_base = apic_base & !0xfff;
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+ println_debug!("IA32_APIC_BASE: {apic_base:#x}");
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+
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+ let apic_base = CachedPP::new(apic_base as usize);
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+ let spurious = apic_base.offset(0xf0).as_ptr::<u32>();
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+ let icr = apic_base.offset(0x300).as_ptr::<u32>();
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+
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+ println_debug!("SPURIOUS: {:#x}", unsafe { spurious.read() });
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+
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+ unsafe { icr.write_volatile(0xc4500) };
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+
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+ while unsafe { icr.read_volatile() } & 0x1000 != 0 {
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+ pause();
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+ }
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+
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+ unsafe { icr.write_volatile(0xc4601) };
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+
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+ while unsafe { icr.read_volatile() } & 0x1000 != 0 {
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+ pause();
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+ }
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+
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+ while AP_COUNT.load(Ordering::Acquire) != 3 {
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+ if BOOT_STACK.load(Ordering::Acquire) == 0 {
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+ let page = Page::alloc_many(9);
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+ let stack_start = page.as_cached().as_ptr::<()>() as usize;
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+ core::mem::forget(page);
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+
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+ BOOT_STACK.store(stack_start, Ordering::Release);
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+ }
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+ pause();
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+ }
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+
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+ println_info!("Processors startup finished");
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+}
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